TSMC Fab Portfolio: Numbers, Locations, and Process Nodes
Last updated onJune 16, 2026
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This page details the manufacturing footprint of Taiwan Semiconductor Manufacturing Company (TSMC, NYSE: TSM).
We present TSMC’s global fabrication network by fab number, physical location, and operational capacity, while highlighting the most advanced process technology nodes currently deployed for high-volume manufacturing.
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For other statistics of TSMC, you may find more information on this page: TSMC key stats.
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To help readers understand the content better, the following terms and glossaries have been provided.
Wafer Fab: A TSMC wafer fab (short for fabrication facility) is an ultra-advanced, highly automated factory owned by Taiwan Semiconductor Manufacturing Company where raw silicon disks, called wafers, are transformed into microscopic computer chips.
Because TSMC is a “pure-play foundry,” its fabs do not design chips. Instead, they act as the physical production engine for the world’s leading fabless tech giants, printing custom-designed processors for companies like Apple, NVIDIA, AMD, and Qualcomm.
Insight & Summary of TSMC’s Debt Due and Liquidity
The following analysis consolidates the trends observed for TSMC’s fab numbers, locations, and the respective technology for volume production as of the fiscal year 2025 (ended on Dec 31, 2025).
35 Years of Fab History: From Legacy to 2nm TSMC’s 16-fab portfolio spans 35 years of semiconductor manufacturing evolution, from Fab 2’s 1990 commencement on 6-inch wafers producing at 450nm to the dual 2nm volume production ramp at Fab 20 and Fab 22 in 2025 — a 225x improvement in linear resolution representing arguably the most sustained technology compounding in any capital-intensive industry.
The wafer size progression tells the structural story: one 6-inch fab (Fab 2, 1990), seven 8-inch fabs (Fab 3 through Fab 16, 1995–2018 across legacy nodes), and eight 12-inch fabs (Fab 12 onwards, 2001–2025) anchoring every advanced and leading-edge node. All fabs commenced since 2001 operate on 300mm (12-inch) wafers, as the cost economics of leading-edge node development at smaller wafer diameters became commercially unviable.
Technology Node Stratification: A Deliberate Portfolio Architecture TSMC’s active fab portfolio is not homogeneous — it is a deliberately stratified architecture spanning five node generations simultaneously. The legacy tier (Fab 2 at 450nm, Fab 3 and Fab 5 at 150nm, Fab 10 at 150nm, Fab 11 at 150nm) provides low-cost capacity for automotive, industrial, IoT, and long-lifecycle semiconductor products where sub-28nm technology is neither required nor economically justified.
The mature tier (Fab 6 and Fab 8 at 110nm, Fab 12 at 40nm) bridges legacy and advanced. The mid-generation tier (Fab 14 and Fab 16 at 16nm, Fab 23 at 28nm) serves the mainstream application processor and automotive market. Above this, the advanced and leading-edge tiers — Fab 15 at 7nm, Fab 21 at 5nm, Fab 18 at 3nm, and the dual 2nm fabs — represent the nodes where semiconductor economics and competitive moats are determined.
The simultaneous operation of nodes from 450nm to 2nm within a single company’s controlled manufacturing network is a strategic asset: TSMC can serve virtually the entire semiconductor ecosystem’s manufacturing requirements from legacy microcontrollers to the most advanced AI accelerators and mobile SoCs, without customers needing to source from multiple foundry partners.
Geographic Diversification: From Taiwanese Concentration to Strategic Globalisation Eleven of TSMC’s 16 fabs are located in Taiwan, concentrated across Hsinchu Science Park (Fab 2, 3, 5, 8, 12, 20), Southern Taiwan Science Park (Fab 6, 14, 18, 22), and Central Taiwan Science Park (Fab 15). This domestic concentration is both TSMC’s historical strength and its most frequently cited geopolitical risk factor.
The remaining five fabs are geographically dispersed in a pattern that has accelerated significantly since 2020: Shanghai, China (Fab 10, 2004, 8-inch, 150nm); Nanjing, China (Fab 16, 2018, 12-inch, 16nm); Washington State, USA (Fab 11, 1998, 8-inch, 150nm); Arizona, USA (Fab 21, 2024, 12-inch, 5nm); and Kumamoto, Japan (Fab 23, 2024, 12-inch, 28nm).
The strategic inflection is visible in the node levels at each geography. TSMC’s China fabs are structurally capped — Fab 10 (legacy 8-inch) and Fab 16 (16nm, now further constrained at 28nm under US export control requirements) cannot access advanced node technology and have become mature-node capacity without growth optionality. Washington State’s Fab 11 (WaferTech, 8-inch, 150nm) is a legacy US asset from 1998 with no advanced node relevance.
The two newest non-Taiwan fabs — Arizona’s Fab 21 (5nm, 2024) and Japan’s Fab 23 (28nm, 2024) — represent TSMC’s response to customer and governmental demand for geographically resilient advanced manufacturing capacity outside Taiwan. Fab 21 at 5nm is the first advanced-node fab TSMC has operated outside Taiwan, though it remains a generation or two behind Fab 18 (3nm) and the 2nm fabs in Hsinchu and Southern Taiwan.
The 2nm Milestone: Dual-Site Production The most strategically significant event in the FY2025 dataset is the simultaneous commencement of 2nm volume production at two sites: Fab 20 in Hsinchu Science Park and Fab 22 in Southern Taiwan Science Park. This dual-site 2nm strategy mirrors what TSMC executed at 3nm (concentrated at Fab 18 in Southern Taiwan) and reflects both capacity scaling requirements for high-demand AI and mobile customers and redundancy planning for Taiwan-specific risk mitigation.
The 2nm node — using Gate-All-Around (GAA) transistor architecture for the first time — represents a major process architecture transition that typically introduces yield challenges in early production. The FY2025 commencement date for both Fab 20 and Fab 22 places TSMC ahead of Samsung (N2 ramp) and Intel (18A) in mass production timelines, reinforcing TSMC’s process leadership position.
Structural Takeaway: TSMC’s fab portfolio as of FY2025 represents three interlocking strategic realities. First, the technology leadership arc — from 7nm (2018) to 5nm (2020) to 3nm (2022) to 2nm (2025) — has been compressed into seven years, with each successive node requiring substantially more capital, process complexity, and EUV lithography intensity.
Second, the geographic profile is in active transition: the next five years will likely see Arizona expand from 5nm toward 3nm or 2nm capability, Japan potentially expand beyond 28nm, and entirely new site decisions in Europe or Southeast Asia. Third, the legacy and mature node fabs — though technologically modest — generate significant free cash flow and serve long-lifecycle customers who cannot or will not migrate to advanced nodes, providing a stable earnings floor that funds the enormous capital requirements of the leading-edge programme.
Most advanced technology reflects the process node in volume production as of December 31, 2025. Legacy fabs may serve specialty and long-lifecycle markets at their respective mature nodes. China fabs (Fab 10, Fab 16) are subject to export control constraints.
1. All financial figures presented were obtained and referenced from TSMC’s annual reports published on the company’s investor relations page: TSMC Annual Reports.
We may use artificial intelligence (AI) tools to assist us in writing some of the text in this article. However, the data is directly obtained from original sources (usually the quarterly and annual reports) and meticulously cross-checked by our editors multiple times to ensure its accuracy and reliability.
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